1. Field of the Invention
The present invention relates to a display device and a manufacturing method of the display device, specifically, a wire technology for the display device.
2. Description of the Related Art
In recent years, flat panel displays (FPDs) typified by liquid crystal display (LCD) devices or electroluminescence (EL) display devices have been attracting attention as display device substitutes for CRTs (Cathode Ray Tubes). In particular, development of a large-screen liquid crystal television set mounted with a large liquid crystal panel which is driven with an active matrix method is the primary task for liquid crystal panel manufacturers. Further, EL televisions having a large screen have been developed actively.
Conventionally, aluminum (Al) is mainly used as a wire material in a liquid crystal display device or an electroluminescence display device. Recently, with the increase in size of display panels, the problem of signal delay has been occurring, due to the increase in the length of wires (also referred to as a wiring) such as gate wires or source wires (also referred to as a gate wiring and a source wiring, respectively).
In order to solve this problem, it is effective to use a material which has lower electrical resistance than aluminum, which is currently used as a wire, for example copper (Cu). However, because copper is an element having mobility, when it is employed as a wire material, deterioration of a semiconductor element becomes a problem. In an integrated circuit, this problem is solved by, for example, a so-called “damascene” method, as shown in Reference 1 (Reference 1: Japanese Published Patent Application No. H 11-45883).
When a “damascene” method is adopted for manufacturing a panel, a polishing process (a planarization process) becomes a problem. In an integrated circuit using a Si wafer, the wafer size is about 300 mmφ, while the glass substrate size is more than 1 square meter, and thus, it is difficult to evenly polish the substrate. For this reason, it is not practical to use the “damascene” method for manufacturing a panel. Therefore, in order to use a copper wire for a panel, instead of the “damascene” method, a wire formation method is needed.
As panels become larger, the length of a leading wire through which a signal from outside the panel passes to be input into a pixel region also becomes a problem. For example, problems such as signal delays or dullness of waveforms occur because the lengths of leading wires (also referred to as a leading wiring) greatly differ among gate wires. For example, in the case of a structure such as that shown in FIG. 13A, because the lengths of a wire 1301 and a wire 1302 differ greatly from each other, the resistance value of each wire differs greatly, and thus, serious signal delay occurs.
In order to solve this problem, in a conventional method, a redundant wire is formed intentionally to make the wire lengths equal, and thus the influence of the delay is reduced. For example, as shown in FIG. 13B, by providing a redundant portion 1303 of the wire, the difference between the lengths of the wire 1301 and the wire 1302 in FIG. 13A is decreased so as to reduce the influence of the delay. However, a large area is needed in order to lead a wire in this method, and it is impossible to make the wire resistances exactly the same.